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FPGA, Quad Channel ADC 180 MSPS

  • Four channel LTC2209 ADC 180 MSPS @ 16-bit resolution
  • Xilinx Virtex-5 FPGA in FF1136 package
  • PCIe x4 or x8, GbE (FPGA programmable)
  • Aurora/SRIO option on lanes 8 to 11 if the PCIe x8 is not utilized

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AMC511 is a Quad ADC (Analog to Digital Converter) module compliant to the AMC.1* and AMC.2 specification. The unit has an on-board, re-configurable FPGA which interfaces directly to the GbE or PCIe bus. The FPGA has an interface to the QDR-II memory (36 and 72-bit wide). This allows for largebuffer sizes to be stored during processing as well as for queuing the data to the host. The AMC511 allows for external clocking as well as internal clocking. The clock goes through an on-board PLL forbuffering/multiplying and jitter cleaner.

The AMC511 has a Trig in/out signal. Each input/output is via an SMB style connector and each of the ADC single ended inputs are converted to differential. The FPGA interfaces directly to the AMC per AMC.1 and/or AMC.2. These interfaces allow customers to use the core to interface to the host with multiple protocols*.*Default configuration is AMC.1 x4 with GbE.

Default configuration is AMC.1 x4 with GbE.

Key Features
  • Four channel LTC2209 ADC 180 MSPS @ 16-bit resolution
  • Xilinx Virtex-5 FPGA in FF1136 package
  • PCIe x4 or x8, GbE (FPGA programmable)
  • Aurora/SRIO option on lanes 8 to 11 if the PCIe x8 is not utilized
  • Quad channel ADC reconfigurable FPGA at 180 MSPS
  • Design utilizes proven VadaTech subcomponents andengineering technique
  • Electrical, mechanical, software, and system-levelexpertise in house
  • Full ecosystem of front and rear boards, enclosures, specialtymodules, and test/dev products from one source
  • AS9100 and ISO9001 certified company

Block diagram

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