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Altera 5SGXEA FPGA AMC Carrier for FMC

  • AMC FPGA based on Altera Stratix-V (5SGXEA) in F1932 package
  • Single module, mid-size or full-size
  • VITA 57.1 FMC HPC Connector (compatible with LPC)
  • All FMC LA, HA, HB pairs routed bi-directionally
  • AMC Ports 0-15, 17-20 and FMC ports DP0-9 are routed for high speed SERDES protocols
  • High-speed SERDES protocols such as PCIe x4, SRIO, XAUI, 1000Base-X are FPGA programmable
  • On board PLL for buffering/multiplying and jitter cleaner (Stratum-3)
  • M-LVDS/LVDS Clock crossbar switch for flexible clock routing
  • 4GB of DDR3 memory to FPGA (4 channels x 1GB each)
  • Serial Over LAN (SOL) with hardware RNG
  • IPMI 2.0 compliant

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The AMC532 is an FPGA based on the Altera Stratix-V 5SGXEA. The module is compliant to the AMC.1, AMC.2, AMC.3 and/or AMC.4 specification. It has an on-board, reconfigurable FPGA which interfaces directly to the AMC backplane and FMC connectors.

The FPGA has interfaces to four banks of DDR3 memory (32-bit wide per bank). This allows for large buffer sizes to be stored during processing as well as for queuing the data to the host.

The AMC532 includes a sophisticated Quad PLL and M-LVDS/LVDS crossbar switch for low-jitter/low-latency clock handling with maximum flexibility between the backplane, FMC, and FPGA. The PLL has an option for Stratum-3 holdover.

The AMC532 has Serial over LAN (SOL) per the IPMI specification and a hardware RNG (Random Number Generator) for secure session to redirect the console serial port of an FPGA-based soft-core CPU.

Key Features
  • AMC FPGA based on Altera Stratix-V (5SGXEA) in F1932 package
  • Single module, mid-size or full-size
  • VITA 57.1 FMC HPC Connector (compatible with LPC)
  • All FMC LA, HA, HB pairs routed bi-directionally
  • AMC Ports 0-15, 17-20 and FMC ports DP0-9 are routed for high speed SERDES protocols
  • High-speed SERDES protocols such as PCIe x4, SRIO, XAUI, 1000Base-X are FPGA programmable
  • On board PLL for buffering/multiplying and jitter cleaner (Stratum-3)
  • M-LVDS/LVDS Clock crossbar switch for flexible clock routing
  • 4GB of DDR3 memory to FPGA (4 channels x 1GB each)
  • Serial Over LAN (SOL) with hardware RNG
  • IPMI 2.0 compliant
Benefits
  • High-performance Altera 5SGXEA FPGA
  • All FMC DP lanes, LA/HA/HB pairs, and clocks are routed from the FMC to the FPGA, providing great flexibility in FMC selection and capabilities
  • Four banks of DDR3 memory allows large buffer sizes and queuing during processing
  • Design utilizes proven VadaTech subcomponents and engineering techniques
  • Electrical, mechanical, software, and system-level expertise in house
  • Full ecosystem of front and rear boards, enclosures, specialty modules, and test/dev products from one source
  • AS9100 and ISO9001 certified company
Specifications
Specifications

Block diagram

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