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AMC 10-channel ADC, MicroTCA.4

  • Double module AMC, compliant to μTCA.4
  • Ten channel of ADC with 125MSPS @ 16-bit resolution utilizing AD9268 device
  • Dual DAC with 250 MSPS @ 16-bit resolution utilizing MAX5878 device (this is user programmable for lower sampling rate)
  • Internal clock or precision external clock from RTM/backplane/front panel clocks
  • Trig in/out configurable by software (external trigger via front or port 17)
  • Backplane PCIe Dual x4 or x8/Dual GbE
  • Xilinx Virtex-6 FPGA in FF1759 package
  • Option for QDR-II+
  • AMC FCLKA, TCLKA, TCLKB, TCLKC and TCLKD are routed
  • Dual SFP+ (up to 6.6Gbps)
  • JTAG selectable front and backplane
  • AMC.1 and AMC.2 (FPGA programmable)

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The AMC520 is a ten-channel ADC (Analog to Digital Converter) with two DAC (Digital to Analog Converter) compliant to the AMC.1 and AMC.2 specification. The unit has an on-board, re-configurable FPGA which interfaces directly to the GbE and PCIe bus.  The FPGA has an interface to the QDR-II+ memory (36 and 72-bit wide). This allows for large buffer sizes to be stored during processing as well as for queuing the data to the host. The AMC520 allows for flexible external clocking as well as internal clocking. The AMC520 has a Trig in/out signal that is sourced from the front panel or port 17. Each input/output goes to the Rear Transition Module (RTM) connector that complies with uTCA.4. Each of the ADC/DAC single ended inputs are converted to differential signals.

The FPGA interfaces directly to the AMC per AMC.1 and AMC.2 and also includes direct front panel interfacing via dual SFP+, raw I/O headers, and LEDs. An RS-232 port is available from the FPGA if the customer desires to implement a soft-processor in the FPGA and have a serial console.

Key Features
  • Double module AMC, compliant to μTCA.4
  • Ten channel of ADC with 125MSPS @ 16-bit resolution utilizing AD9268 device
  • Dual DAC with 250 MSPS @ 16-bit resolution utilizing MAX5878 device (this is user programmable for lower sampling rate)
  • Internal clock or precision external clock from RTM/backplane/front panel clocks
  • Trig in/out configurable by software (external trigger via front or port 17)
  • Backplane PCIe Dual x4 or x8/Dual GbE
  • Xilinx Virtex-6 FPGA in FF1759 package
  • Option for QDR-II+
  • AMC FCLKA, TCLKA, TCLKB, TCLKC and TCLKD are routed
  • Dual SFP+ (up to 6.6Gbps)
  • JTAG selectable front and backplane
  • AMC.1 and AMC.2 (FPGA programmable)
Benefits
  • Digital converter to MicroTCA.4 specifications, up to 250 MSPS (DAC)
  • Multiple banks of QDR-II+ memory allows buffering and queuing during processing for efficient operation
  • Design utilizes proven VadaTech subcomponents and engineering techniques
  • Electrical, mechanical, software, and system-level
    expertise in house
  • AS9100 and ISO9001 certified company
Specifications
Specifications

Block diagram

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