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Dual ADC, 12-bit @ 4.0 GSPS, FMC

  • FPGA Mezzanine Card (FMC) per VITA 57
  • Dual Texas Instruments ADC12J4000 ADC
    • Four JESD204B lanes per ADC are routed to the FMC connector
    • Usable output bandwidth of 800 MHz at 4x decimation and 4000 MSPS
    • Usable output bandwidth of 100 MHz at 32x decimation and 4000 MSPS
  • Supported by DAQ Series™ data acquisition software
  • Excellent dynamic performance
  • Front panel interface includes CLK In, Trig In, Analog In, and GPIO
  • Ultra Low-Noise wide-band PLL

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The FMC226 is an FPGA Mezzanine Carrier (FMC) per VITA 57 specification. The board has dual ADC with 12-bit resolution at 4.0 GSPS.

The FMC226 utilizes a dual TI ADC12J4000 ADC providing 12-bit conversion rates of up to 4.0 GSPS. The analog input, clock input and trigger inputs of the FMC226 are routed via SSMC connectors. The internal clock frequency is programmable and the clock is capable of locking to an external reference.

Key Features
  • FPGA Mezzanine Card (FMC) per VITA 57
  • Dual Texas Instruments ADC12J4000 ADC
    • Four JESD204B lanes per ADC are routed to the FMC connector
    • Usable output bandwidth of 800 MHz at 4x decimation and 4000 MSPS
    • Usable output bandwidth of 100 MHz at 32x decimation and 4000 MSPS
  • Supported by DAQ Series™ data acquisition software
  • Excellent dynamic performance
  • Front panel interface includes CLK In, Trig In, Analog In, and GPIO
  • Ultra Low-Noise wide-band PLL
Benefits
  • Array of FMC’s and FMC carriers available from VadaTech
  • High dynamic range for versatility in video/broadcast requirements
  • Ideal for Broadband communications systems, Wireless infrastructure, LTE, ATE, RADAR/Jamming
  • Electrical, mechanical, software, and system-level expertise in house
  • Full system supply from the industry leader
  • AS9100 and ISO9001 certified company
Specifications
Specifications

Block diagram

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