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AMC Dual ADC, Virtex-7, 12-Bit @ 2.6 GSPS

  • Single module, mid-size per AMC.0• Conduction cooled version available
  • Dual AD9625 ADC, 12-Bit @ 2.6 GSPS in single module, mid-size
  • Xilinx Virtex-7 690T FPGA in FFG-1761 package
  • Quad bank QDR-II+ memory (576 Mb total) and 1Gb DDR3
  • AMC Ports 4-11 are routed to FPGA per AMC.1, AMC.2 and AMC.4 (PCIe, SRIO, XAUI, etc. are FPGA programmable)
  • AMC Ports 12-15 and 17-20 optionally routed to the FPGA
  • Internal, external or backplane clock with on-board wide-band PLL
  • IPMI 2.0 compliant

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The AMC526 provides dual-channel ADC with sample rates up to 2.6 GSPS, making it suitable for signal capture/analysis applications such as COMINT/SIGINT, radar, research and instrumentation. The on-board Virtex-7 690T is suitable for local signal processing and data reduction prior to transfer out via the backplane using PCIe, SRIO or Ethernet.

The AMC ports 12-15 and 17-20 are optionally routed to the FPGA from the AMC connector, providing the user with flexibility to support custom high-bandwidth interconnects between compatible FPGA modules (depending on backplane capabilities). The FPGA is supported by FLASH memory for boot image storage, four banks of QDR-II+ for fast data buffering and a further bank of DDR3 for local data.

TCLK A-D are routed to the FPGA via an on-board clock and jitter cleaner while FCLK is routed directly. The module includes a very flexible clocking sub-system, supporting internal or external (backplane or front panel) clock source with internal PLL/jitter cleaner.

The AMC526 is available in both air-cooled (MTCA.0 and MTCA.1) and rugged conduction cooled(MTCA.2 or MTCA.3) versions.

Key Features
  • Single module, mid-size per AMC.0• Conduction cooled version available
  • Dual AD9625 ADC, 12-Bit @ 2.6 GSPS in single module, mid-size
  • Xilinx Virtex-7 690T FPGA in FFG-1761 package
  • Quad bank QDR-II+ memory (576 Mb total) and 1Gb DDR3
  • AMC Ports 4-11 are routed to FPGA per AMC.1, AMC.2 and AMC.4 (PCIe, SRIO, XAUI, etc. are FPGA programmable)
  • AMC Ports 12-15 and 17-20 optionally routed to the FPGA
  • Internal, external or backplane clock with on-board wide-band PLL
  • IPMI 2.0 compliant
Benefits
  • High performance ADC (AD9625)
  • Flexible clocking
  • Fast local buffer (36-bit wide)
  • BSP support and example code
  • Strong mil/aero support
  • Electrical, mechanical, software, and system-level expertise in house
  • Full system supply from industry leader
  • AS9100 and ISO9001 certified company
Specifications
Specifications

Block diagram

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