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Quad ADC 12-bit @ 1 GSPS, FMC

  • FPGA Mezzanine Card (FMC) per VITA 57
  • Quad ADC based on AD9234 (1 GSPS or 500 MSPS)
    • Optional decimate-by-2 DDC per channel
    • JESD204B
    • 2 GHz analog input full power bandwidth
  • Option for Direct RF sampling clock via front panel
  • Supported by DAQ Series™ data acquisition software
  • On board wide-band PLL
  • Trig In/Out
  • CLK In

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The FMC228 is an FPGA Mezzanine Card (FMC) per VITA 57 specification. The module utilizes dual AD9234 ADCs (1 GSPS or 500 MSPS)  providing two inputs per ADC with 12-bit conversion rates of up to 1.0 GSPS.

The front panel RF clock is a reference input clock to the PLL or it could input to the ADC direct sampling clock. The PLL can also receive its reference clock from an on board or the FMC Carrier. The front panel also has Trig In/Out and CLK In ports.

Key Features
  • FPGA Mezzanine Card (FMC) per VITA 57
  • Quad ADC based on AD9234 (1 GSPS or 500 MSPS)
    • Optional decimate-by-2 DDC per channel
    • JESD204B
    • 2 GHz analog input full power bandwidth
  • Option for Direct RF sampling clock via front panel
  • Supported by DAQ Series™ data acquisition software
  • On board wide-band PLL
  • Trig In/Out
  • CLK In
Benefits
  • Array of FMC’s and FMC carriers available from VadaTech
  • Design utilizes proven VadaTech subcomponents and engineering techniques
  • Electrical, mechanical, software, and system-level expertise in house
  • Full system supply from the industry leader
  • AS9100 and ISO9001 certified company
Specifications
Specifications

Block diagram

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