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FMC ADC 12-bit @ 4.0 GSPS, DAC 12-bit @ 4.5 GSPS

  • FPGA Mezzanine Card (FMC) per VITA 57
  • TI ADC12J4000 ADC
  • E2V EV12DS400 DAC
  • Excellent dynamic performance
  • Front panel interface includes CLK In, Trig In, AnalogIn/Out, and GPIO
  • Ultra Low-Noise wide-band PLL
  • On-chip delay locked loops (DLLs) optimize timing between different clock domains.

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The FMC215 is an FPGA Mezzanine Module per VITA 57 specification that provides a single ADC at 4 GSPS and a single DAC at 4.5 GSPS. The module is suitable for signal capture and low-latency feedback applications such as COMINT/SIGINT, radar, jamming, research and instrumentation.

The FMC215 utilizes TI ADC12J4000 ADC providing 12-bit conversion at rates of 1.0 to 4.0 GSPS with a full-power input bandwidth of 3.2 GHz and offering configurable DDC (digital down conversion). The E2V EV12DS400 DAC provides 12-bit conversion at rates of up to 4.5 GSPS with output bandwidth up to 7 GHz.

The FMC215 has a trigger input which is routed to the FMC connector as well as to the ADC.The analog input/output, clock input and trigger inputs are routed via SSMC connectors.

Key Features
  • FPGA Mezzanine Card (FMC) per VITA 57
  • TI ADC12J4000 ADC
  • E2V EV12DS400 DAC
  • Excellent dynamic performance
  • Front panel interface includes CLK In, Trig In, AnalogIn/Out, and GPIO
  • Ultra Low-Noise wide-band PLL
  • On-chip delay locked loops (DLLs) optimize timing between different clock domains.
Benefits
  • High dynamic range for versatility in video/broadcastrequirements
  • Ideal for Broadband communications systems, Wirelessinfrastructure, LTE, ATE, RADAR/Jamming
  • Strong mil/aero support
  • Electrical, mechanical, software, and system-level expertisein house
  • Full system supply from industry leader
  • AS9100 and ISO9001 certified company
Specifications
Specifications

Block diagram

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