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FPGA Virtex UltraScale™ XCVU440 with P2040 and PinoutPlus™

  • Xilinx Ultra Scale XCVU440 w/ QorIQ PPC2040
  • 8 GB of DDR-4 (single bank of 64-bits)
  • 20 SERDES lanes optionally routed to Tongue 2
  • Ideal for ASIC prototyping/emulation
  • AMC Ports 4-11 are routed to FPGA per AMC.1, AMC.2 and AMC.4 (protocols such as PCIe, SRIO, 10GbE/40GbE, etc. are FPGA programmable)
  • AMC Ports 12-15 and 17-20 are routed to the FPGA
  • AMC FCLKA, TCLKA, TCLKB, TCLKC and TCLKD are routed
  • Clock jitter cleaner
  • Single module, mid-size AMC (full-size optional)

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The AMC596 is based on the Virtex UltraScale™ XCVU440 FPGA in FLGA2892 package withan on board Power PC P2040. The AMC596 is compliant to the AMC.1, AMC.2, AMC.3 and/orAMC.4 specification.

The module provides 20 SERDES lanes on tongue 2, providing high-bandwidth connectivity toanother module at a very high speed (where supported by appropriate chassis). The use of thetongue 2 connector complies with the AMC.0 specification.

The on-board, re-configurable FPGA interfaces to the AMC FCLKA and TCLKA-D via a MLVDSCross Bar Switch (CBS). The FPGA has interface to one DDR4, 64-bit wide, with 8 GB totalmemory. This allows for large buffer sizes to be stored during processing as well as for queuingthe data to the host.

The on-board quad core P2040 runs at 1.2 GHz with 1 GB of DDR3, 128 MB of Boot Flash, anda 32 GB SD Card. The PPC has x4 PCIe interface to the FPGA in addition to its local bus. ThePPC has its dual GbE routed to ports 0 and 1 of the AMC via a mux to allow FPGA routing tothe ports as well. The same applies to ports 2-3 (PPC SATA ports or directly to the FPGA viamux selection).

Key Features
  • Xilinx Ultra Scale XCVU440 w/ QorIQ PPC2040
  • 8 GB of DDR-4 (single bank of 64-bits)
  • 20 SERDES lanes optionally routed to Tongue 2
  • Ideal for ASIC prototyping/emulation
  • AMC Ports 4-11 are routed to FPGA per AMC.1, AMC.2 and AMC.4 (protocols such as PCIe, SRIO, 10GbE/40GbE, etc. are FPGA programmable)
  • AMC Ports 12-15 and 17-20 are routed to the FPGA
  • AMC FCLKA, TCLKA, TCLKB, TCLKC and TCLKD are routed
  • Clock jitter cleaner
  • Single module, mid-size AMC (full-size optional)
Benefits
  • Xilinx Virtex-7 XCVU440 FPGA in FLGA2892 package
  • Single Bank of 64-bit wide DDR4 memory allows larger buffer sizes while processing and queuing data to the host
  • Optional Tongue 2 routing for high-bandwidth connectivity to neighboring slot
  • Electrical, mechanical, software, and system-level expertise in house
  • Full system supply from industry leader
  • AS9100 and ISO9001 certified company
Specifications
Specifications

Block diagram

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