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FMC ADC 12-bit @ 2.6 GSPS and DAC 14-bit @ 5.6 GSPS

NEW
  • ADC AD9625
    • 8 JESD204B lanes from the ADC isrouted to the FMC
    • 12-bit at 2.6 GSPS
    • Wide full power bandwidth supports IF sampling of signals up to 2 GHz
  • DAC AD9129
    • 14-bit at 5.6 GSPS
  • FPGA Mezzanine Card (FMC) per VITA 57
  • Excellent dynamic performance
  • Front panel interface includes CLK In, Trig Inand Trig Out

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The FMC216 is an FPGA Mezzanine Card (FMC) per VITA 57 specification. The FMC216 utilizes AD9625 ADCs providing 12-bit conversion rates of up to 2.6 GSPS and a DAC AD9129 providing 14-bit conversion rates of up to 5.6 GSPS.

The analog input/output, digital output, clock and trigger interfaces of theFMC216 are routed via SSMC connectors. The internal clock frequency is programmable and the clock is capable of locking to an external reference.

Key Features
  • ADC AD9625
    • 8 JESD204B lanes from the ADC isrouted to the FMC
    • 12-bit at 2.6 GSPS
    • Wide full power bandwidth supports IF sampling of signals up to 2 GHz
  • DAC AD9129
    • 14-bit at 5.6 GSPS
  • FPGA Mezzanine Card (FMC) per VITA 57
  • Excellent dynamic performance
  • Front panel interface includes CLK In, Trig Inand Trig Out
Benefits
  • High dynamic range for versatility in video/broadcast requirements
  • Ideal for Broadband communications systems, Wireless infrastructure, LTE, ATE, RADAR/Jamming
  • Compatible with a broad range of Xilinx- and Altera-based FMC carriers from VadaTech and others
  • Electrical, mechanical, software, and systemlevelexpertise in house
  • Full system supply from industry leader
  • AS9100 and ISO9001 certified company
Specifications
Specifications

Block diagram

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