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FMC ADC 12-bit @ 6.4 GSPS and DAC 16-bit @ 12 GSPS

NEW
  • ADC ADC12DJ3200
    • Option for ADC12DJ270 or ADC12DJ1600
    • 8 JESD204B lanes from the ADC is routed to the FMC
    • 12-bit at 6.4 GSPS
    • Wide full power bandwidth supports IF sampling of signals up to 6 GHz
  • DAC AD9164/AD9162
    • 16-bit at 12 GSPS
  • FPGA Mezzanine Card (FMC) per VITA 57
  • Excellent dynamic performance
  • Front panel interface includes CLK In, Trig In and Trig Out

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The FMC217 is an FPGA Mezzanine Card (FMC) per VITA 57 specification. The board has a dual channel ADC and single channel DAC.

The FMC217 utilizes TI ADC12DJ3200 ADC (with option forADC12DJ2700 or ADC12DJ1600) providing 12-bit conversion rates of up to 6.4 GSPS and a DAC AD9164 (option for AD9162) providing 16-bit conversion rates of up to 12 GSPS. The ADC in non-interleaving mode can have two separate inputs each at 3.2 GSPS.

The analog input/output, clock and trigger interfaces of the FMC217 are routed via SSMC connectors. The internal clock frequency is programmable and the clock is capable of locking to an external reference.

Key Features
  • ADC ADC12DJ3200
    • Option for ADC12DJ270 or ADC12DJ1600
    • 8 JESD204B lanes from the ADC is routed to the FMC
    • 12-bit at 6.4 GSPS
    • Wide full power bandwidth supports IF sampling of signals up to 6 GHz
  • DAC AD9164/AD9162
    • 16-bit at 12 GSPS
  • FPGA Mezzanine Card (FMC) per VITA 57
  • Excellent dynamic performance
  • Front panel interface includes CLK In, Trig In and Trig Out
Benefits
  • High dynamic range for versatility in video/broadcast requirements
  • Ideal for Broadband communications systems, Wireless infrastructure, LTE, ATE, RADAR/Jamming
  • Compatible with a broad range of Xilinx- and Altera based FMC carriers from VadaTech and others
  • Electrical, mechanical, software, and system-level expertise in house
  • Full system supply from industry leader
  • AS9100 and ISO9001 certified company
Specifications
Specifications

Block diagram

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