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Altera Carrier for FMC, Stratix® V (5SGXEA)

  • Single module, mid-size or full-size
  • AMC FPGA based on Altera Stratix® V (5SGXEA) in F1932 package
  • VITA 57.1 FMC HPC Connector (compatible with LPC)
  • AMC Ports 0-15, 17-20 and FMC Ports DP0-9 are routed for high speed SERDES protocols
  • All FMC LA, HA, HB pairs routed bi-directionally
  • High-speed SERDES protocols such as PCIe x4, SRIO, XAUI, 1000Base-X are FPGA programmable
  • Onboard PLL for buffering/multiplying and jitter cleaner (Stratum-3)
  • M-LVDS/LVDS Clock crossbar switch for flexible clock routing
  • 4 GB of DDR3 memory to FPGA (4 channels x 1 GB each)
  • Serial Over LAN (SOL) with hardware RNG

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The AMC532 is an FPGA based on the Altera Stratix® V 5SGXEA and is compliant to AMC.1, AMC.2, AMC.3 and/or AMC.4 specifications.

The onboard, re-configurable FPGA interfaces directly to the AMC backplane, FMC connectors and four banks of DDR3 memory (32-bit wide per bank). This allows for large buffer sizes to be stored during processing as well as for queuing the data to the host.

The unit includes a sophisticated Quad PLL and M-LVDS/LVDS Cross Bar Switch (CBS) for low-jitter/low-latency clock handling with maximum flexibility between the backplane, FMC, and FPGA. The PLL has an option for Stratum-3 holdover.

AMC532 has Serial over LAN (SOL) per the IPMI specification and a hardware Random Number Generator (RNG) for secure session to redirect the console serial port of an FPGA-based soft-core CPU.

The AMC532 supports a wide range of VadaTech FMCs that include: FMC102, FMC103, FMC104, FMC105, FMC106, FMC107, FMC108, FMC109, FMC210, FMC211, FMC218, FMC219, FMC225 and FMC226.

 VIDEO: Intel FPGA solutions at VadaTech: This video introduces the advantages of using VadaTech to build your new products embedding Intel FPGA SoC.

 

Key Features
  • Single module, mid-size or full-size
  • AMC FPGA based on Altera Stratix® V (5SGXEA) in F1932 package
  • VITA 57.1 FMC HPC Connector (compatible with LPC)
  • AMC Ports 0-15, 17-20 and FMC Ports DP0-9 are routed for high speed SERDES protocols
  • All FMC LA, HA, HB pairs routed bi-directionally
  • High-speed SERDES protocols such as PCIe x4, SRIO, XAUI, 1000Base-X are FPGA programmable
  • Onboard PLL for buffering/multiplying and jitter cleaner (Stratum-3)
  • M-LVDS/LVDS Clock crossbar switch for flexible clock routing
  • 4 GB of DDR3 memory to FPGA (4 channels x 1 GB each)
  • Serial Over LAN (SOL) with hardware RNG
Benefits
  • All FMC DP lanes, LA/HA/HB pairs, and clocks are routed from the FMC to the FPGA, providing great flexibility in FMC selection and capabilities
  • Electrical, mechanical, software, and system-level expertise in house
  • Full system supply from industry leader
  • AS9100 and ISO9001 certified company
Specifications
Specifications

Block diagram

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