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FMC212

Dual ADC 12-bit @ 1.5 GSPS and Dual DAC 16-bit @ 2 8 GSPS, FMC

  • Dual ADC 12-bit @ 1.5 GSPS (EV12AS200AZP)
  • The ADC has Full power input Bandwidth at 1.5 GSPS is 2.3 GHz and very low latency < 5 Clock Cycles
  • Dual DAC 16-bit @ 2.8 GSPS (TI DAC39J82)
  • FPGA Mezzanine Card (FMC) per VITA 57
  • Front panel interface includes RF CLK In, Trig In/Out

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The FMC212 is an FPGA Mezzanine Card per VITA 57 specification with high-speed dual ADC and dual DAC.

The ADC is based on the e2v EV12AS200AZP that provides two analog inputs with 12-bit resolution at 1.5 GSPS.

The DAC is based on the TI DAC39J82 that provides two analog outputs with 16-bit resolution at 2.8 GSPS.

The module has a wideband PLL for RF sampling clock. The wideband PLL has RF reference clocking which can come from the FMC carrier or from the front panel via the Ref CLK In Port.

 

Key Features
  • Dual ADC 12-bit @ 1.5 GSPS (EV12AS200AZP)
  • The ADC has Full power input Bandwidth at 1.5 GSPS is 2.3 GHz and very low latency < 5 Clock Cycles
  • Dual DAC 16-bit @ 2.8 GSPS (TI DAC39J82)
  • FPGA Mezzanine Card (FMC) per VITA 57
  • Front panel interface includes RF CLK In, Trig In/Out
Benefits
  • Electrical, mechanical, software, and system-level expertise in house
  • Full system supply from industry leader
  • AS9100 and ISO9001 certified company
Specifications
Specifications

Block diagram

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