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Altera Carrier for FMC, Stratix-10™

  • Altera Stratix-10 (Option for GX1650 or GX2800)
  • AMC Ports 4-11 are routed to FPGA per AMC.1, AMC.2 and AMC.4
  • AMC Ports 12-15 and 17-20 are routed to the FPGA
  • Single module, mid-size AMC (full-size optional)
  • AMC FCLKA, TCLKA, TCLKB, TCLKC and TCLKD are routed
  • Clock jitter cleaner
  • 16 GB of DDR-4 (dual bank of 64-bits)

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The AMC538 is based on the Altera Stratix-10™ GX1650/2800 FPGA. The AMC538 is compliant to the AMC.1, AMC.2, AMC.3 and/or AMC.4 specification.

The module routes all LA/HA/HB and 10 DP SERDES to the FMC slot. The on-board, re-configurable FPGA interfaces directly to the AMC FCLKA  and TCLKA–D via a Cross Bar Switch (CBS) MLVDS.

The FPGA has two banks of DDR4, 64-bit wide, with 16 GB total memory. This allows for large buffer sizes to be stored during processing as well as for queuing the data to the host.

 

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Key Features
  • Altera Stratix-10 (Option for GX1650 or GX2800)
  • AMC Ports 4-11 are routed to FPGA per AMC.1, AMC.2 and AMC.4
  • AMC Ports 12-15 and 17-20 are routed to the FPGA
  • Single module, mid-size AMC (full-size optional)
  • AMC FCLKA, TCLKA, TCLKB, TCLKC and TCLKD are routed
  • Clock jitter cleaner
  • 16 GB of DDR-4 (dual bank of 64-bits)
Benefits
  • Stratix-10 FPGA
  • Dual Bank of 64-bit wide DDR4 memory allows larger buffer sizes while processing and queuing data to the host
  • Electrical, mechanical, software, and system-level expertise in house
  • Full system supply from industry leader
  • AS9100 and ISO9001 certified company
Specifications
Specifications

Block diagram

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View product UTC004 Data Sheet

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