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VPX599A

Dual ADC @ 6.4 GSPS and Dual DAC @ 12 GSPS, UltraScale™, 3U VPX

  • 3U FPGA Dual ADC and Dual DAC per VITA 46
  • Xilinx Kintex UltraScale™ XCKU115 FPGA
  • Dual ADC 12-bit @ 6.4 GSPS or quad ADC at 3.2 GSPS with TI ADC12DJ3200
  • Option for ADC12DJ3200 or ADC12DJ2700
  • Dual DAC 16-bit @ 12 GSPS (AD9162 or AD9164)
  • High-performance clock jitter cleaner
  • VHDL reference design with source code
  • Protocols such as PCIe, SRIO, 10GbE/40GbE, etc. are FPGA programmable
  • Dual bank 16 GB of DDR4 Memory total (64-bit wide)
  • Health Management through dedicated Processor

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The VPX599A provides dual ADC with sampling rates of up to 6.4 GSPS at a 12-bit resolution (TI ADC12DJ3200 or ADC12DJ2700). Also, dual DAC delivers update rates of up to 12 GSPS and incorporates direct RF synthesis capable of 6 GSPS at a 16-bit resolution (Analog Devices AD9162 or AD9164). This makes VPX599A suitable for signal capture/analysis applications such as COMINT/SIGINT, radar, research and instrumentation.

The unit has an on-board Kintex UltraScale™ XCKU115 FPGA that directly interface with ADC/DAC and two banks of 64-bit wide DDR4 memory channels with a total of 16 GB memory.

The module routes to the P1 connectors x16 high speed SERDES that could be configured as PCIe/SRIO/10GbE/Aurora, etc. To the P2 the module routes an additional x8 SERDES as well as x16 GPIO and x8 LVDS. The module has an onboard dedicated health management CPU which complies with the OpenVPX standard

The unit is available in a range of temperature and shock/vib specifications per ANSI/VITA 47, up to V3 and OS2.

Please contact VadaTech for details of Conduction Cooled versions.

Key Features
  • 3U FPGA Dual ADC and Dual DAC per VITA 46
  • Xilinx Kintex UltraScale™ XCKU115 FPGA
  • Dual ADC 12-bit @ 6.4 GSPS or quad ADC at 3.2 GSPS with TI ADC12DJ3200
  • Option for ADC12DJ3200 or ADC12DJ2700
  • Dual DAC 16-bit @ 12 GSPS (AD9162 or AD9164)
  • High-performance clock jitter cleaner
  • VHDL reference design with source code
  • Protocols such as PCIe, SRIO, 10GbE/40GbE, etc. are FPGA programmable
  • Dual bank 16 GB of DDR4 Memory total (64-bit wide)
  • Health Management through dedicated Processor
Benefits
  • RADAR data processing
  • Reference design with VHDL source code speeds application development
  • Full system supply from industry leader
  • AS9100 and ISO9001 certified company
Specifications
Specifications

Block diagram

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