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ADC 12-bit @ 5.4 GSPS and DAC 14-bit @ 4 GSPS, RF Sampling at 20GHz, UltraScale+, 3U VPX

  • ADC 12-bit @ 5.4 GSPS (EV12AS350A)
  • DAC 14-bit @ 4 GSPS (RDA414M4RF) with 20 GHz RF Clocking
  • The DAC has programmable Return to Zero Output for Multiple Nyquist Operation
  • Xilinx UltraScale+ XCVU13P FPGA with 8 GB DDR4
  • Supported by development accelerator software package for Multi-Path Modulation
  • Health Management through dedicated Processor

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The VPX573 provides an ADC with sampling rates of up to 5.4 GSPS at a 12-bit resolution (EV12AS350A) and a DAC that delivers update rates of up to 4 GSPS at a 14-bit resolution (RDA414M4RF).

The DAC is a MUXDAC with the RF clock to the DAC at 20 GHz. The DAC supports Multiple Return to Zero (MRZ) waveform modulation enabling it to operate in multiple Nyquist bands. It also has a low latency of 2 data clock cycles. By choosing the ratio between RFCLK and DCLK, it is possible to create an operating band anywhere up to 20 GHz with the RDA414M4RF.

Both Converters have parallel interface to the FPGA, avoiding latency associated with serializing/deserializing data.

The XCVU13P FPGA has large 360 Mb on-chip UltraRAM which, with the ADC and DAC selection, makes this module ideal for low-latency applications such as DRFM, radar simulators and smart jammers.

The FPGA interfaces directly to rear I/O via SERDES and LVDS, supporting PCIe, SRIO, GbE/10GbE/40GbE or Aurora backplane connections. General purpose I/O signals, e.g. for trigger, are routed to the front panel that also contains 8 LED/Bi-color.

ADC and DAC have a separate sampling clock utilizing the wide-band PLL, which is locked to a reference clock sourced from front panel or backplane.

The VPX573 includes platform health management/monitoring capability using VadaTech’s field-proven IPMI software. An onboard management controller has the ability to access board sensors and manage FPGA image updates.

The unit is available in a range of temperature and shock/vib specifications per ANSI/VITA 47, up to V3 and OS2.

Key Features
  • ADC 12-bit @ 5.4 GSPS (EV12AS350A)
  • DAC 14-bit @ 4 GSPS (RDA414M4RF) with 20 GHz RF Clocking
  • The DAC has programmable Return to Zero Output for Multiple Nyquist Operation
  • Xilinx UltraScale+ XCVU13P FPGA with 8 GB DDR4
  • Supported by development accelerator software package for Multi-Path Modulation
  • Health Management through dedicated Processor
Benefits
  • Very low latency from ADC to DAC
  • XCVU13P has large internal memory
  • Reference design with VHDL source code speeds application development
  • Electrical, mechanical, software, and system-level expertise in house
  • Full system supply from industry leader
  • AS9100 and ISO9001 certified company
Specifications
Specifications

Block diagram

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