FPGA/FMC Carrier, Kintex UltraScale™, 3U VPX

  • 3U FPGA carrier for FPGA Mezzanine Card (FMC) per VITA 46 and VITA 57
  • Xilinx Kintex UltraScale™  XCKU115 FPGA
  • High-performance clock jitter cleaner
  • VHDL reference design with source code
  • Protocols such as PCIe, SRIO, 10GbE/40GbE, etc. are FPGA programmable
  • Compatible with VadaTech and 3rd party FMCs
  • 20 GB of DDR4 Memory (2 banks of 64-bit wide, and single bank of 32-bit wide)
  • Health Management through dedicated Processor

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The VPX592 is a FPGA Carrier (VITA 46) with an FMC (VITA 57) interface. The unit has an onboard, re-configurable Xilinx Kintex UltraScale™ XCKU115 FPGA which has 5520 DSP Slices. The FPGA interfaces directly to the FMC DP 0-9 and all FMC LA/HA/HB pairs

The VPX592 routes high-speed serial links directly from the FPGA to backplane,allowing the core to interface directly to the host with protocols such as 40 GbE, 10 GbE, PCIe or SRIO. The FPGA has 2 banks of 64-bit and singlebank of 32-bit wide DDR4 memory (20 GB total). This allows for large buffer sizes to be stored during processing as well as for queuing the data to the host.

The module supports dual GbE and, dependent on FPGA code loaded, PCIe up to Gen3 (dual x4 or x8 lane), or dual SRIO, 10GbE or 40GbE on P1. There are dual x4 lanes routed to P2 for direct FPGA-to-FPGA connection using lightweight protocols such as Aurora (backplane dependent) and additional 16 LVDS pairs are routed to P2.

The unit is available in a range of temperature and shock/vib spcifiations per ANSI/VITA 47, up to V3 and OS2.

Key Features
  • 3U FPGA carrier for FPGA Mezzanine Card (FMC) per VITA 46 and VITA 57
  • Xilinx Kintex UltraScale™  XCKU115 FPGA
  • High-performance clock jitter cleaner
  • VHDL reference design with source code
  • Protocols such as PCIe, SRIO, 10GbE/40GbE, etc. are FPGA programmable
  • Compatible with VadaTech and 3rd party FMCs
  • 20 GB of DDR4 Memory (2 banks of 64-bit wide, and single bank of 32-bit wide)
  • Health Management through dedicated Processor
Benefits
  • XCKU115 FPGA provides 5,520 DSP slices for complex processing
  • 20 GBytes of DDR-4 memory for fast local data buffering
  • Reference design with VHDL source code speeds application development
  • Electrical, mechanical, software, and system-level expertise in house
  • Full system supply from industry leader
  • AS9100 and ISO9001 certified company
Specifications
Specifications

Block diagram

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