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ADC @ 56 GSPS, 2 or 4 Channel, UltraScale, AMC

  • Double module, mid-size or full-size
  • Xilinx UltraScale™ XCVU190 FPGA
  • ADC 8-bit @ up to dual 56 GSPS
  • 2 x 56 or 4 x 28 GSPS channels
  • ADC is 65 nm CMOS process technology
  • 16 GB of DDR4 Memory (2 banks of 64-bit)
  • Very low power consumption (5W for the ADC)
  • Calibration warning and over-range flags
  • –3 dB analog input bandwidth nominally 15 GHz
  • Internal 14 GHz VCO/PLL per I/Q ADC pair
  • Differential analog input: 1.0V PPD
  • Tongue 2 for additional SERDES

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The AMC591 used the Fujitsu MB8AC2070 ADC (Analog to Digital Converter) to provide dual 56 GSPS or quad 28 GSPS from four channels ADC (user selectable). The board is compliant to AMC.0 specifications.

The AMC591 allows the implementation of extremely fast, high-resolution ADCs in CMOS process technology. The ADC is ideal for applications that require ultra-high performance analog and digital processing such as 100G applications. Achieved input bandwidth depends on system configuration and operating conditions, contact VadaTech for details.

The AMC591 has a Xilinx UltraScale™ XCVU190 FPGA which has 1800 DSP Slices. The FPGA interfaces directly to the AMC connectors over both tongue 1 and tongue 2, supporting up to 22 lanes routed to GTY transceivers for board-to-board connectivity (chassis dependent). The FPGA has 2 banks of 64-bit DDR4 memory (16 GB total).

The tongue 2 connections can also provide dedicated lanes to communicate with high speed processors such as VadaTech AMC750/AMC751. Chassis such as the VadaTech VT884/VT815 can accept modules with Tongue two connector.

The Module has two routing options for high speed SERDES from the FPGA to the backplane:

  • Option B = 0 most of the SERDES are routed to Tongue 2 (Figure 2)
  • Option B = 1 most of the SERDES are routed to Tongue 1 (Figure 3)

This allows the module to provide the most flexibility depending on the chassis routing.

Key Features
  • Double module, mid-size or full-size
  • Xilinx UltraScale™ XCVU190 FPGA
  • ADC 8-bit @ up to dual 56 GSPS
  • 2 x 56 or 4 x 28 GSPS channels
  • ADC is 65 nm CMOS process technology
  • 16 GB of DDR4 Memory (2 banks of 64-bit)
  • Very low power consumption (5W for the ADC)
  • Calibration warning and over-range flags
  • –3 dB analog input bandwidth nominally 15 GHz
  • Internal 14 GHz VCO/PLL per I/Q ADC pair
  • Differential analog input: 1.0V PPD
  • Tongue 2 for additional SERDES
Benefits
  • Highest sampling rate for the module size in the industry
  • Uses MB8AC2070 ADC
  • Low power consumption – CMOS process technology
  • Flexible selection of sample rate and channel count
  • Electrical, mechanical, software, and system-level expertise in house
  • Full system supply from industry leader
  • AS9100 and ISO9001 certified company
Specifications
Specifications

Block diagram

Block diagram

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