FMC IRIG-B Module

  • FPGA Mezzanine Card (FMC) compatible with VITA 57.1
  • Single-module
  • Input for 1PPS, 10 MHz or IRIG-B
  • Module or DC level shift IRIG-B per 200-04
  • Encode the year (2 digits) through second of the preceding 1PPS
  • On board Dual DPLL/IEEE 1588 1 PPS Synchronize and Jitter Cleaner
  • RoHS compliant

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The FMC150 is an FPGA Mezzanine Module per VITA 57 specification. The FMC150 has a 1PPS, 10 MHz Sine Wave or IRIG-B input.

The FMC150 provides the signals to the FPGA from which the firmware will decoded the IRIG-B data to set second’s year digits only.

The 3 inputs will be used along with front end parts and the FPGA to control a time-decade clock that will have 16 BCD digits: 1 digit of the year of the decade, 3 digits of days, 2 digits of hours, 2 digits of minutes, 2 digits of seconds and 6 digits of microseconds.

The module has on board Dual DPLL/IEEE 1588 with 1PPS Synchronize and Jitter Cleaner. The Dual DPLL synchronizes 1Hz to 750MHz, providing frequency with jitter cleaning of noisy references. Complies with ITU-T G.8286 and Telcordia GR-253. The module has Automatic and manual holdover, and reference switch over providing zero delay and hitless/phase buildout operation.

The Module outputs any clock output frequency thru its on board PLL.

Key Features
  • FPGA Mezzanine Card (FMC) compatible with VITA 57.1
  • Single-module
  • Input for 1PPS, 10 MHz or IRIG-B
  • Module or DC level shift IRIG-B per 200-04
  • Encode the year (2 digits) through second of the preceding 1PPS
  • On board Dual DPLL/IEEE 1588 1 PPS Synchronize and Jitter Cleaner
  • RoHS compliant
Benefits
  • Design utilizes proven VadaTech subcomponents and engineering techniques
  • Electrical, mechanical, software, and system-level expertise in house
  • Full system supply from industry leader
  • AS9100 and ISO9001 certified company
Specifications
Specifications

Block diagram

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