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You are here: HomeProductsFMC VITA 57A/D & D/AFMC A/D D/AFMC225

FMC225

(similar products)

12-bit 4.0 GSPS ADC and 14-bit 5.7 GSPS DAC, FMC

FPGA Mezzanine Card (FMC) per VITA 57
TI ADC12J4000 ADC
- Usable output bandwidth of 800 MHz at 4x decimation and 4000 MSPS
- Usable output bandwidth of 100 MHz at 32x decimation and 4000 MSPS
- Bypass Mode for full Nyquist output bandwidth
Analog Devices AD9129 DAC
- DC-to-1.4 GHz in Baseband mode
- DC-to-1.0 GHz in 2x Interpolation mode
- 1.4 to 4.2 GHz in Mix-Mode
Supported by DAQ Series™ data acquisition software
Excellent dynamic performance
Front panel interface includes CLK In, Trig In, Analog In/Out, and GPIO
Ultra Low-Noise wide-band PLL
On-chip delay locked loops (DLLs) optimize timing between different clock domains.

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The FMC225 is an FPGA Mezzanine Module per VITA 57 specification. The FMC225 has an ADC 12-bit at 4.0 GSPS and a DAC 14-bit at 2.85 GSPS direct RF synthesis.

The FMC225 utilizes TI ADC12J4000 ADC providing 12-bit conversion at rates of up to 4.0 GSPS and an Analog Devices AD9129 DAC providing 14-bit conversion at rates of up to 2.85 GSPS. The DAC core is based on a quad-switch architecture that enables dualedge clocking operation, effectively increasing the DAC update rate to 5.7 GSPS when configured for Mix-Mode™ or 2x interpolation. The input sampling clock can be via thefront panel or the on board wide-band PLL. The FMC225 has a trigger input which is routed to the FMC connector as well as to the ADC.

The analog input/output, clock input and trigger inputs are routed via SSMC connectors.

Key Features

FPGA Mezzanine Card (FMC) per VITA 57
TI ADC12J4000 ADC
- Usable output bandwidth of 800 MHz at 4x decimation and 4000 MSPS
- Usable output bandwidth of 100 MHz at 32x decimation and 4000 MSPS
- Bypass Mode for full Nyquist output bandwidth
Analog Devices AD9129 DAC
- DC-to-1.4 GHz in Baseband mode
- DC-to-1.0 GHz in 2x Interpolation mode
- 1.4 to 4.2 GHz in Mix-Mode
Supported by DAQ Series™ data acquisition software
Excellent dynamic performance
Front panel interface includes CLK In, Trig In, Analog In/Out, and GPIO
Ultra Low-Noise wide-band PLL
On-chip delay locked loops (DLLs) optimize timing between different clock domains.

Benefits

Array of FMC’s and FMC carriers available from VadaTech
High dynamic range for versatility in video/broadcast requirements
Ideal for Broadband communications systems, Wirelessi nfrastructure, LTE, ATE, RADAR/Jamming
Electrical, mechanical, software, and system-level expertise in house
Full system supply from the industry leader
AS9100 and ISO9001 certified company

Specifications

Block diagram

AMC516

Virtex-7 FPGA Carrier for FMC, AMC

AMC FPGA carrier for FMC per VITA-57
Xilinx Virtex-7 690T FPGA in FFG-1761 package with optional P2040
Supported by DAQ Series™ data acquisition software
AMC Ports 12-15 and 17-20 are routed to the FPGA
AMC Ports 4-11 are routed to FPGA per AMC.1, AMC.2 and AMC.4 (protocols such as PCIe, SRIO, XAUI, etc. are FPGA programmable)
AMC FCLKA, TCLKA, TCLKB, TCLKC and TCLKD are routed
Single module, mid-size AMC (full-size optional)
Clock jitter cleaner
IPMI 2.0 compliant

View product AMC516 Data Sheet

AMC530

Altera EP4S100G AMC FPGA

Altera Stratix IV Device EP4S100Gx in 1517 pin count (40mm x 40mm)
AMC Ports 2-3 and 4-11 are routed to FPGA (protocols such as PCIe, SRIO, XAUI, etc. are FPGA programmable)
Ports 0 and 1 are Muxed with P2020 GbE
AMC FCLKA, TCLKA, TCLKB, TCLKC and TCLKD are routed
On board PLL for buffering/multiplying and jitter cleaner
Option for up to 16GB of DDR3 memory to the FPGA
Three banks of QDR-II+ each 72-bit wide
Option for on board Freescale QorIQ PPC2020 with up to 4GB DDR3

View product AMC530 Data Sheet

FMC210

FMC ADC 10-bit @ 2.6 GSPS Module

FPGA Mezzanine Card (FMC) per VITA-57
Single ADC EV10AS150B @2.5 GSPS
Single module
5 GHz Full Power Input Bandwidth (-3dB)
True single core architecture (no calibration required)
External Interleaving:Full scale analog input Voltage Span 500mVpp
- Gain Adjust
- Offset Adjust
- Sampling Delay Adjust
All front panel input/outputs are via MMCX:
- Analog Input
- Reference clock
- Trig in/out
- General purpose I/O
Super low phase noise RF PLL Synthesizer

View product FMC210 Data Sheet

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FMC225

12-bit 4.0 GSPS ADC and 14-bit 5.7 GSPS DAC, FMC

Block diagram

AMC516

Virtex-7 FPGA Carrier for FMC, AMC

AMC530

Altera EP4S100G AMC FPGA

FMC210

FMC ADC 10-bit @ 2.6 GSPS Module

Info request

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Register

Change Password

Forgot Password

Choose your region:

By Part Number

By Function

By Architecture

Software & Tools

Design Services/Custom Products

Products DownloadCenter Portal

FMC225

12-bit 4.0 GSPS ADC and 14-bit 5.7 GSPS DAC, FMC

Block diagram

AMC516

Virtex-7 FPGA Carrier for FMC, AMC

AMC530

Altera EP4S100G AMC FPGA

FMC210

FMC ADC 10-bit @ 2.6 GSPS Module

Info request

Design Services/
Custom Products

Products Download
Center Portal