32x ECL or NECL Input with Clock synchronization and Dual ADC
The FMC152 is an FPGA Mezzanine Card (FMC) per VITA 57.1 standard (see comment below) offering a small footprint and allowing for general ECL or NECL 32x parallel data input with synchronization.
There are two HMCAD1511 ADC on board to monitor the clock inputs. The FMC152 has low pass filers on board to clean the 1PPS, the dual 100MHz as well as the 10MHz clock before the input of the ADC.
Clocks and Data are input to the FMC152 via dual high-density connectors.
This Module does not follow the VITA57 height constrain. It has an additional connector on the back of the FMC to accommodate the I/O. For example, on the AMC FPGA FMC Carriers, it requires a full-height AMC panel to accommodate all the I/Os. The Carrier must have a monolithic panel (the FMC152 does not come with an FMC panel) to cover the FMC152 I/O envelope.
Key Features
- 32 x ECL or NECL Receiver with clock synchronization
- Dual HMCAD1511 ADC to monitor clock input accuracy
- 10MHz Clock Input
- 100Mhz Clock Input
- 1PPS Clock Input
- IRIG-B Clock Input (Digital)
- User LED
Benefits
- Single module to receive ECL/NEC Parallel data
- Utilizing commercially-available, standard high-density connector for ease of cabling
- All I/O types utilize differential signaling between the transceivers on the FMC and the FPGA on the carrier for optimal signal integrity across the FMC connector
- Electrical, mechanical, software, and system-level expertise in house
- Full system supply from industry leader
- AS9100 and ISO9001 certified company
Specifications
Block diagram
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