FMC160

The FMC160 is an FPGA Mezzanine Module per VITA 57 specification providing a complete timing solution. The FMC160 has 1PPS, Sine Wave clock, IRIG-B input, IRIG-B out and a GbE.

The module can take its upstream time/frequency from one of:

• GPS (freq and time + location/velocity/other metadata)
• IEEE1588 PTP (freq and time)
• IRIG-B AM/DCLS/Manchester (freq and time)
• 1PPS (freq only)
• Sine Wave Clock In (freq only)
• Synchronous Ethernet (freq only, can be combined with IEEE1588 PTP)
• Carrier board 1PPS via FMC connector (freq only)

The module can provide its downstream time/frequency to all of:

• IEEE1588 PTP (freq and time)
• IRIG-B AM/DCLS/Manchester (freq and time)
• 1PPS (freq only, can be combined with
• NMEA for freq and time) NMEA (time only, can be combined with 1PPS for freq and time)
• Clock Out (freq only)
• Synchronous Ethernet (freq only)
• Carrier board Host interface and clocks via FMC connector

The standard firmware on the FMC160 interfaces to the carrier FPGA through SPI for obtaining time/location/velocity metadata.  But additional hardware interfaces are available such as PCIe, Ethernet, Aurora, etc.  Contact VadaTech if you have an interest in interfacing to the FMC160 via these additional protocols via the FMC connector.

The module has an on board 5 x DPLL. The DPLL synchronizes 1Hz to 750MHz, providing frequency with jitter cleaning of noisy references. Complies with ITU-T G.8286, G.813, G. 812 and Telcordia GR-253/GR-1244. The module will automatically holdover upon loss of reference while still providing its time/frequency outputs to the rest of the system.  The DPLL allows for fast lock to 1HZ input taking only 3 to 60 seconds depending on the reference input compared to 10 minutes or more for previous solutions.

The FMC160 provides standard NMEA format via RS-232 for external devices.

The FMC160 provides synchronized clock to the carrier thru its CLK0 and CLK1. The FMC160 has CLK2 and CLK3 routed to the DPLL as an input reference option. The Module also routes from the DPLL to the LA00/LA17 clock pins.

The FMC160-resident firmware binaries are provided by VadaTech and customer development is not expected for the FMC160 itself.  Customer development is expected for the FPGA on the FMC carrier board, but reference design source code will be made available to provide an example of how to interface to the FMC160 host interface (SPI + Clocks/1PPS). The module also interfaces to the carrier with SERDES on DP0/1 as well as DP4/5.