The VPX242 is a 3U VPX module per VITA 46. The modules bring four SERDES from the P1 connector to four SFP+ ports in the front. The VPX242 allows for any protocol (Ethernet, Aurora, etc.) to run at 10G down to 1G.
The module has Clock Data Recovery on board (CDR) for better signal integrity.
Key Features
- 3U VPX form factor
- x4 SERDES from P1 (any lane from 1 to 16) to four SFP+ ports
- Allows for 10G down to 1G speed
- Health Management through dedicated Processor
Benefits
- Electrical, mechanical, software, and system-level expertise in house
- Full system supply from industry leader
- AS9100 and ISO9001 certified company
Related Products
VPX516
3U FPGA Carrier for FMC, Xilinx Virtex-7, 3U VPX
- 3U FPGA carrier for FPGA Mezzanine Card (FMC) per VITA 46 and VITA 57
- Xilinx Virtex-7 690T FPGA in FFG-1761 package
- High-performance clock jitter cleaner
- VHDL reference design with source code
- Protocols such as PCIe, SRIO, 10GbE/40GbE, etc. are FPGA programmable
- Compatible with VadaTech and 3rd party FMCs
- 2.5 GB of DDR3 Memory
- Health Management through dedicated Processor
View product
VPX516 Data Sheet
VPX592
FPGA/FMC Carrier, Kintex UltraScale™, 3U VPX
- 3U FPGA carrier for FPGA Mezzanine Card (FMC) per VITA 46 and VITA 57
- Xilinx Kintex UltraScale™ XCKU115 FPGA
- High-performance clock jitter cleaner
- VHDL reference design with source code
- Protocols such as PCIe, SRIO, 10GbE/40GbE, etc. are FPGA programmable
- Compatible with VadaTech and 3rd party FMCs
- 20 GB of DDR4 Memory (2 banks of 64-bit wide, and single bank of 32-bit wide)
- Health Management through dedicated Processor
View product
VPX592 Data Sheet
VPX599
Dual ADC @ 10.4 or 6.4 GSPS and Dual DAC @ 12 GSPS, UltraScale™, 3U VPX
- 3U FPGA Dual ADC and Dual DAC per VITA 46
- Xilinx Kintex UltraScale™ XCKU115 FPGA
- Dual ADC 12-bit @ 10.4/6.4 GSPS or quad ADC @ 5.2/3.2 GSPS with TI ADC12DJ5200 or ADC12DJ3200
- Option for ADC12DJ5200, ADC12DJ3200 or ADC12DJ2700
- Dual DAC 16-bit @ 12 GSPS (AD9162 or AD9164) or TI DAC38RF82 14-bit @ 9GSPS
- High-performance clock jitter cleaner
- VHDL reference design with source code
- Protocols such as PCIe, SRIO, 10GbE/40GbE, etc. are FPGA programmable
- 16 GB of DDR4 Memory (64-bit wide)
- Health Management through dedicated Processor
View product
VPX599 Data Sheet
Info request
Create a list of products to inquire about for more information or quote request.
