FMC121

The FMC121 is a FPGA Mezzanine Card (FMC) compatible with VITA 57.1 FMC carriers. It has two zSFP+/SFP28 cages which allows for Dual optics to be routed to DP0+/- and DP4+/- pins.

The FMC121 is protocol-agnostic and has a low jitter fractional PLL which can lock to CLK2 and CLK3 coming from the Carrier or be free running. The fractional PLL can generate two separate clocks to the two GBT clock pins and can provide two more additional clocks on CLK0 and CLK1 for the carrier. Further the PLL could also synchronize to an external clock source via its front panel SSMC.