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You are here: HomeProductsMicroTCA/AMCA/D & D/AAMC FPGA A/D D/A AMC598

AMC598

Quad ADC @ 3 GSPS with Quad DAC @ 12 GSPS, Kintex UltraScale, AMC

  • Xilinx UltraScale™ XCKU115 FPGA
  • Quad ADC 14-bit @ 3 GSPS (AD9208) (Option for Octal ADC with no DAC)
  • Quad DAC channels 16-bit @ 12 GSPS (AD9162 or AD9164) (Option for Octal DAC with no ADC)
  • Two banks of 64-bit wide and a single bank of 32-bit wide DDR4 for a total of 20 GB
  • AMC Ports 4-11 are routed to FPGA per AMC.1, AMC.2 and AMC.4 (protocols such as PCIe, SRIO, 1/10/40GbE, etc. are FPGA programmable)
  • AMC FCLKA, TCLKA, TCLKB, TCLKC and TCLKD are routed
  • Clock Jitter cleaner
  • Option for Direct RF Clock sampling for the ADC/DAC
  • IPMI 2.0 compliant

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The AMC598 provides quad ADC with sampling rates of up to 3 GSPS at a 14-bit resolution (AD9208 with the option for up to Octal ADC). Also, a quad DAC delivers update rates of up to 12 GSPS and direct RF synthesis at 6 GSPS at a 16-bit resolution (Analog Devices AD9162 or AD9164 with the option for up to Octal DAC). This makes AMC598 suitable for signal capture/analysis applications such as COMINT/SIGINT, radar, research and instrumentation.

The unit has an on-board, re-configurable UltraScale™ XCKU115 FPGA that directly interfaces with ADC/DAC and three banks of DDR4 memory channels (dual 64-bit wide and a single bank of 32-bit for a total of 20 GB). This allows for large buffer sizes to be stored during processing as well as for queuing the data to the host.

The AMC598 8 HP panel size will occupy two mid-size slots in a chassis.

 

Key Features
  • Xilinx UltraScale™ XCKU115 FPGA
  • Quad ADC 14-bit @ 3 GSPS (AD9208) (Option for Octal ADC with no DAC)
  • Quad DAC channels 16-bit @ 12 GSPS (AD9162 or AD9164) (Option for Octal DAC with no ADC)
  • Two banks of 64-bit wide and a single bank of 32-bit wide DDR4 for a total of 20 GB
  • AMC Ports 4-11 are routed to FPGA per AMC.1, AMC.2 and AMC.4 (protocols such as PCIe, SRIO, 1/10/40GbE, etc. are FPGA programmable)
  • AMC FCLKA, TCLKA, TCLKB, TCLKC and TCLKD are routed
  • Clock Jitter cleaner
  • Option for Direct RF Clock sampling for the ADC/DAC
  • IPMI 2.0 compliant
Benefits
  • Closely coupled ADC and DAC for low-latency response, dual channel for I/Q
  • Sampling rate >6 GSPS for radar and EW applications
  • Xilinx UltraScale™ XCKU115 FPGA provides powerful compute resource
  • Electrical, mechanical, software, and system-level expertise in house
  • Full system supply from industry leader
  • AS9100 and ISO9001 certified company
Specifications
Specifications

Block diagram

Block diagram

Block diagram

Block diagram

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