VPX599
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Dual ADC @ 10.4 or 6.4 GSPS and Dual DAC @ 12 GSPS, UltraScale™, 3U VPX
- 3U FPGA Dual ADC and Dual DAC per VITA 46
- Xilinx Kintex UltraScale™ XCKU115 FPGA
- Dual ADC 12-bit @ 10.4/6.4 GSPS or quad ADC @ 5.2/3.2 GSPS with TI ADC12DJ5200 or ADC12DJ3200
- Option for ADC12DJ5200, ADC12DJ3200 or ADC12DJ2700
- Dual DAC 16-bit @ 12 GSPS (AD9162 or AD9164) or TI DAC38RF82 14-bit @ 9GSPS
- High-performance clock jitter cleaner
- VHDL reference design with source code
- Protocols such as PCIe, SRIO, 10GbE/40GbE, etc. are FPGA programmable
- 16 GB of DDR4 Memory (64-bit wide)
- Health Management through dedicated Processor
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The VPX599 provides dual ADC with sampling rates of up to 10.4/6.4 GSPS at a 12-bit resolution (TI ADC12DJ5200, ADC12DJ3200 or ADC12DJ2700). Also, dual DAC delivers update rates of up to 12 GSPS and incorporates direct RF synthesis capable of 6 GSPS at a 16-bit resolution (Analog Devices AD9162 or AD9164) or 9 GSPS with TI DAC38RF82. This makes VPX599 suitable for signal capture/analysis applications such as COMINT/SIGINT, radar, research and instrumentation.
The unit has an onboard Kintex UltraScale™ XCKU115 FPGA that directly interface with ADC/DAC and two banks of 64-bit wide DDR4 memory channels with a total of 16 GB memory.
The module routes to the P1/P2 connectors Quad GbE, x16 high speed SERDES that can be configured as PCIe/SRIO/40GbE/10GbE/Aurora, GPIO, etc. The module has an onboard dedicated health management CPU which complies with the OpenVPX standard.
The unit is available in a range of temperature and shock/vib specifications per ANSI/VITA 47, up to V3 and OS2.
Please contact VadaTech for details of Conduction Cooled versions.
Key Features
- 3U FPGA Dual ADC and Dual DAC per VITA 46
- Xilinx Kintex UltraScale™ XCKU115 FPGA
- Dual ADC 12-bit @ 10.4/6.4 GSPS or quad ADC @ 5.2/3.2 GSPS with TI ADC12DJ5200 or ADC12DJ3200
- Option for ADC12DJ5200, ADC12DJ3200 or ADC12DJ2700
- Dual DAC 16-bit @ 12 GSPS (AD9162 or AD9164) or TI DAC38RF82 14-bit @ 9GSPS
- High-performance clock jitter cleaner
- VHDL reference design with source code
- Protocols such as PCIe, SRIO, 10GbE/40GbE, etc. are FPGA programmable
- 16 GB of DDR4 Memory (64-bit wide)
- Health Management through dedicated Processor
Benefits
- RADAR data processing
- Reference design with VHDL source code speeds application development
- Electrical, mechanical, software, and system-level expertise in house
- Full system supply from industry leader
- AS9100 and ISO9001 certified company
Specifications
Block diagram
Related Products
VPX516
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- High-performance clock jitter cleaner
- VHDL reference design with source code
- Protocols such as PCIe, SRIO, 10GbE/40GbE, etc. are FPGA programmable
- Compatible with VadaTech and 3rd party FMCs
- 2.5 GB of DDR3 Memory
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VPX517
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- High-performance clock jitter cleaner
- VHDL reference design with source code
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- Compatible with VadaTech and 3rd party FMCs
- Health Management through dedicated Processor
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VPX592
FPGA/FMC Carrier, Kintex UltraScale™, 3U VPX
- 3U FPGA carrier for FPGA Mezzanine Card (FMC) per VITA 46 and VITA 57
- Xilinx Kintex UltraScale™ XCKU115 FPGA
- High-performance clock jitter cleaner
- VHDL reference design with source code
- Protocols such as PCIe, SRIO, 10GbE/40GbE, etc. are FPGA programmable
- Compatible with VadaTech and 3rd party FMCs
- 20 GB of DDR4 Memory (2 banks of 64-bit wide, and single bank of 32-bit wide)
- Health Management through dedicated Processor
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VPX592 Data Sheet
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