VPX572

The VPX572 provides a dual ADC with sampling rates of up to 6.4 GSPS at 12-bit resolution (ADC12DJ3200). The ADCs could be configured to run as quad channel each running at 3.2 GSPS.

The XCVU13P FPGA has large 360 Mb on-chip UltraRAM which is excellent for radar simulators and smart jammers. The FPGA interfaces directly to rear I/O via SERDES and LVDS, supporting PCIe, SRIO, GbE/10GbE/40GbE or Aurora backplane connections. General purpose I/O signals, e.g. for trigger, are routed to the front panel that also contains 8 LED/Bi-color.

ADCs have a common sampling rate, which can be fed from front panel (Direct RF Clock) or from PLL locked to a 10/100 MHz reference clock sourced from front panel or backplane. Sampling clock selection is by ordering option. The sampling on the ADCs are fully coherent with each other.

The VPX572 includes platform health management/monitoring capability using VadaTech’s field-proven IPMI software. An on-board management controller has the ability to access board sensors and manage FPGA image updates.

The unit is available in a range of temperature and shock/vib specifications per ANSI/VITA 47, up to V3 and OS2.