VPX582

The VPX582 provides octal integrated RF transceivers based on Analog Device AD9371 or AD9375. The module is compatible with Analog Devices design tools. The RX RF front end is designed for the L1/L5 Band and it has a filter and amplifier per each RX input. The VPX582 comes with option for input RF of 800Mhz to 2.8GHz without the filters.

VPX582 is based on Xilinx UltraScale+ XCZU15EG MPSoC FPGA, which has 3528 DSP Slices and 746k logic cells. The XCZU15EG includes quad-core ARM application processor, dual-core ARM real-time processor and Mali™ graphics processing unit, as well as over 26 Mb of block RAM and 31 Mb of UltraRAM.

The Module routes its RF TX/RX to the front panel. The VPX582 has 8 TX/RX SERDES, Dual GbE as 1000Base-BX, Dual GbE as 10/100/1000Base-TX, x2 PCIe from PS, 8 LVDS (could be configured as singled ended), 16 +3.3V GPIO, CPU RS-232 and management RS-232 to the P1/P2 connector.

Each of the receiver side (RX) have an L1/L5 band filter followed by with an LNA (Low Noise Amplifier). Each of the transmitter side (TX) have the output go thru the L1/L5 band filter.

The ARM processor interface to the 8GB of DDR-4 memory with ECC and the FPGA interfaces to a single DDR4 memory channel (64-bit wide). This allows for large buffer sizes to be stored during processing as well as for queuing the data to the host.

The module has on board 64 GB of Flash and 128 MB of Boot Flash.