VPX577

The VPX577 provides Quad ADC with sampling rates of up to 10.4 GSPS at 12-bit resolution utilizing the TI ADC12DJ5200. Each ADC is configurable to run as dual channel at half the sampling rate (5.2 GSPS) to provide Octal channels.  

The module has Dual DAC based on TI DAC38RF82 with 14-bit at 9 GSPS.

Interfacing to the FPGA is a 64-bit dual bank of DDR-4 memory with 8GB per bank.

The XCVU13P FPGA contains large 360 Mb on-chip UltraRAM, excellent for radar simulators and smart jammers. The FPGA interfaces directly to rear I/O via SERDES and LVDS, supporting PCIe, SRIO, GbE/10GbE/40GbE/100GbE or Aurora backplane connections. General purpose I/O are routed to the P2.

ADCs have a common sampling rate from common PLL locked to a 10/100 MHz reference clock sourced from front panel or backplane. The sampling clock on the ADCs are fully coherent with each other. The DAC have a coherent sampling clock as well.  

The VPX577 has two routing option for the ADC/DAC interfacing to the FPGA. Option E = 0 connects dual ADC and a single DAC on the top SLR region and dual ADC and single DAC on the bottom SLR region. Option E = 1 connects all four ADC on the top SLR region and dual DAC on the bottom SLR region.

The Module has a Zynq UltraScale+ FPGA on board. The Zynq has dual GbE to the P1 as well as x2 SERDES to the P1 which could be configured as PCIe.  The Zynq interfaces to the Virtex FPGA via PCIe x1 with PCIe Tandem Configuration capability, additional x2 SERDES, and GPIO.

The VPX577 includes platform health management/monitoring capability using VadaTech’s field-proven IPMI software. An onboard management controller has the ability to access board sensors and manage FPGA image updates.

The unit is available in a range of temperature and shock/vib specifications per ANSI/VITA 47, up to V3 and OS2.